XNFPREP For Design lfsr.xff
From XNFPREP Version 5.1.0

1995/04/09 17:24:46

Xilinx, Inc.

XNFPREP For Design lfsr.xff Page i

Table of Contents
-----------------

XNFPREP Errors .................................................. 1

XNFPREP Warnings ................................................ 2

Clock Signals Report ............................................ 3

Logic Trimming .................................................. 4

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XNFPREP Errors
--------------
No XNFPREP errors were issued.

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XNFPREP Warnings
----------------
XNFPREP: WARNING 3684:
All of the external outputs in this design are using
slew-rate-limited output drivers.

The delay on speed critical outputs can be dramatically reduced by
designating them as fast outputs in the schematic.

However, you should be careful not to designate too many outputs
which switch together as fast because this can cause excessive
ground bounce. For more information on this subject refer to the
IOB switching characteristic guidelines for the device which you
are using.

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Clock Signals Report
--------------------

The following clock signals were found in the design:

Driver = GCLK ; Fan Out = 4 ; Signal Name = N68

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Logic Trimming
--------------

This chapter shows the logic removed from your design due to
sourceless or loadless signals and VCC or ground connections. If the
removal of a signal or symbol results in the subsequent removal of an
additional signal or symbol, the message explaining that second
removal will be indented. This indentation will be repeated as a
chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of
logic, look at the lines which begin at the leftmost edge of the page
below.

BUFG symbol 'U27/$1I19' (driving signal 'N68') converted to
architecture specific GCLK clock symbol.