-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC3.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC3.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP19.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC3
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Sat Mar  4 02:29:04 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC3 is
   port (
      BCD_IN_3, BCD_IN_2, BCD_IN_1, BCD_IN_0 : in std_logic ;
      SSD_OUT_6, SSD_OUT_5, SSD_OUT_4, SSD_OUT_3, SSD_OUT_2, SSD_OUT_1, 
      SSD_OUT_0 : out std_logic) ;
end LOGIC3 ;

architecture exemplar of LOGIC3 is
   signal
      vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, vh_10, 
      vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_24: std_logic ;
 
begin
   g1000 : AND4I1 port map ( Q=>vh_0, A=>BCD_IN_2, B=>BCD_IN_0, C=>BCD_IN_1, D=>BCD_IN_3);
   g1001 : AND4I3 port map ( Q=>vh_1, A=>BCD_IN_2, B=>BCD_IN_3, C=>BCD_IN_1, D=>BCD_IN_0);
   g1002 : AND4I3 port map ( Q=>vh_2, A=>BCD_IN_1, B=>BCD_IN_2, C=>BCD_IN_0, D=>BCD_IN_3);
   g1003 : AND2I2 port map ( Q=>vh_3, A=>vh_1, B=>vh_2);
   g1004 : AND4I3 port map ( Q=>vh_4, A=>BCD_IN_3, B=>BCD_IN_2, C=>BCD_IN_0, D=>BCD_IN_1);
   g1005 : AND2I2 port map ( Q=>vh_5, A=>BCD_IN_3, B=>BCD_IN_1);
   g1006 : AND3I2 port map ( Q=>vh_6, A=>vh_5, B=>BCD_IN_2, C=>BCD_IN_0);
   g1007 : AND2I2 port map ( Q=>vh_7, A=>vh_4, B=>vh_6);
   g1008 : AND4I2 port map ( Q=>vh_8, A=>BCD_IN_1, B=>BCD_IN_2, C=>BCD_IN_0, D=>BCD_IN_3);
   g1009 : AND4I2 port map ( Q=>vh_9, A=>BCD_IN_2, B=>BCD_IN_0, C=>BCD_IN_1, D=>BCD_IN_3);
   g1010 : AND2I2 port map ( Q=>vh_10, A=>vh_8, B=>vh_9);
   g1011 : AND4I2 port map ( Q=>vh_11, A=>BCD_IN_3, B=>BCD_IN_0, C=>BCD_IN_1, D=>BCD_IN_2);
   g1012 : MUX2X3 port map ( Q=>vh_12, A=>BCD_IN_3, B=>BCD_IN_3, S=>BCD_IN_1 );
   g1013 : AND3I1 port map ( Q=>vh_13, A=>vh_12, B=>BCD_IN_0, C=>BCD_IN_2);
   g1014 : AND5I3 port map ( Q=>vh_14, A=>vh_7, B=>vh_3, C=>vh_13, D=>vh_0, E=>vh_11);
   g1015 : AND2I0 port map ( Q=>vh_15, A=>vh_14, B=>vh_10);
   g1016 : AND4I2 port map ( Q=>vh_16, A=>vh_7, B=>vh_10, C=>vh_11, D=>vh_15 );
   g1017 : AND2I0 port map ( Q=>vh_17, A=>vh_3, B=>vh_16);
   g1018 : OR2I1 port map ( Q=>SSD_OUT_6, A=>vh_0, B=>vh_17);
   g1019 : INV port map ( Q=>SSD_OUT_5, A=>vh_14);
   g1020 : INV port map ( Q=>SSD_OUT_4, A=>vh_15);
   g1021 : INV port map ( Q=>SSD_OUT_3, A=>vh_17);
   g1022 : OR3I1 port map ( Q=>SSD_OUT_2, A=>vh_8, B=>vh_15, C=>vh_7);
   g1023 : INV port map ( Q=>SSD_OUT_1, A=>vh_16);
   g1024 : AND5I3 port map ( Q=>vh_24, A=>vh_3, B=>vh_10, C=>vh_4, D=>vh_11, E=>vh_15);
   g1025 : INV port map ( Q=>SSD_OUT_0, A=>vh_24);

end exemplar ;