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<P><FONT SIZE=6>Other Models and Packages</FONT></P>
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Some of the documents in this section contain live references, or pointers, to information created and maintained by other institutions. Please note that SCRA & DARPA do not control and cannot guarantee the relevance, timeliness, accuracy, or even the continued existence of these outside materials.
Errors may be brought to our attention via
<A HREF="mailto:info@scra.org?SUBJECT=VHDL ERRORS -- standards_working_group.html Page">Webmaster</A> and
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SCRA & DARPA do not guarantee, warrant, vouch for or endorse any of the material
(Software, VHDL Models or Course Modules, etc) that may be found on this server or on any
server pointed to by this server. The material may not have been tested or may not have been
tested completely and if used it is at the users own risk.
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This code is provided as-is with no warranty of any kind with regard to this material, either
expressed or implied, including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. For limitations and restrictions on using this material
see the <a href="/legal-stuff/disclaimer.html">DISCLAIMER </a>page.
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<ul>
<p>
<li> <a href="http://eecad.sogang.ac.kr/~chang/vhdl/Welcome.html">VHDL Examples for Synthesis</a>
<ul>
<li><b>Description :</b> Contains examples for synthesis of a latch,
<li> flipflop with asynchronous reset, flipflop with synchronous reset,
<li> tri-state buffer, decoder, mux, bidirectional buffer, and a FSM
<li> General Taxonomy Level : Behavioral
<li> Created by :
</ul>
<p>
<li> <a href="http://www.doulos.co.uk/models/index.htm">VHDL Model Library by Doulos</a><IMG SRC="../../graphics/new-small.gif" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Contains models which include
<li> <a href="http://www.doulos.co.uk/models/model_9711.htm">32-bit Demultiplexer</a>, <a href="http://www.doulos.co.uk/models/model_9603.htm">Generic RAM Model</a>, <a href="http://www.doulos.co.uk/models/model_9604.htm">8-bit Analog-to-Digital Converter</a>,
<li> <a href="http://www.doulos.co.uk/models/model_9605.htm">Finite Impulse Response (FIR) Filter</a>,
<li> <a href="http://www.doulos.co.uk/models/model_9607.htm">Image Processing Cache Register Array (IPCRA)</a>
<li> <a href="http://www.doulos.co.uk/models/model_9608.htm">Carry Look Ahead Blocks</a>, <a href="http://www.doulos.co.uk/models/model_9609.htm">Synchronizer Scaler</a>,
<li> <a href="http://www.doulos.co.uk/models/model_9610.htm">HeapSortParallel</a>, <a href="http://www.doulos.co.uk/models/model_9701.htm">Simple RAM Model</a>, and <a href="http://www.doulos.co.uk/models/model_9703.htm">Spectrum Spreader</a>
<li> Advanced VHDL Techniques (AVT)
<li> General Taxonomy Level : Behavioral
<li> Maintained by : <a href="http://www.doulos.co.uk/">Doulos</a>: (V)HDL training and consultancy organization
</ul>
<p>
<li> <a href="http://www.cs.adelaide.edu.au/users/petera/designers-guide/DG-source.html">The Designer's Guide to VHDL : Source Code</a>
<ul>
<li><b>Description :</b> Source Code and Test Benches from the book "The designer's Guide to VHDL"
<li> General Taxonomy Level : Behavioral and RTL
<li> Created by : Peter J. Ashenden
</ul>
<p>
<li> <A HREF="other/boardlevel.tar.gz">Complete Board Level Modeling example using the ESA board level modeling guidelines</A> - a compressed tar file
<ul>
<li><b>Description :</b> Board Level Modeling Example
<li> See the board level modeling guidelines for a description
<UL>
<LI><A HREF="other/boardlevel.pdf">View PDF</A>
<LI><A HREF="other/BoardLevel.ps">postscript</A>
<LI><A HREF="other/BoardLevel_ps.gz">gzipped postscript</A>
</UL>
<li> General Taxonomy Level : Behavioral
<li> Created by : European Space Agency
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/dresistor.vhd">Resistor Model</a>
<ul>
<li><b>Description :</b> Digital view of a resistor
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/dcapacitor.vhd">Capacitor Model</a>
<ul>
<li><b>Description :</b> Digital view of a capacitor ( an open circuit )
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/dgnd.vhd">Ground Model</a>
<ul>
<li><b>Description :</b> Source of simulation value GND -> std_logic '0'
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/cdc339.vhd">Clock Driver</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Clock driver with 3-state outputs
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/jumper.vhd">Jumper</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Circuit board jumper gap
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/pull.vhd">Pull-up or Pull-down model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> PULL-UP or PULL-DOWN
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/roboclock.vhd">Skew Clock Buffer model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Programmable Skew Clock Buffer
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/sc0900.vhd">Variable Amplitude Driver model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Variable Amplitude Driver
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/semirigid.vhd">Delay Line model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Delay Line
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/vbb.vhd">VBB source model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Source of simulation value VBB -> std_logic 'W'
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/vcc.vhd">VCC source model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Source of simulation value VCC -> std_logic '1'
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/vee.vhd">VEE source model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Source of simulation value VEE -> std_logic '0'
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<li> FTP to VHDL.ORG site - <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/misc/vtt.vhd">VTT source model</a><IMG SRC="../../graphics/new-small.gif" ALT="new" WIDTH=28 HEIGHT=11 BORDER=0>
<ul>
<li><b>Description :</b> Source of simulation value VTT -> std_logic '0'
<li></B>Accompanying Packages Required : <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Download Packages</a>
<li> General Taxonomy Level : Behavioral
<li> Created by : Free Model Foundation
</ul>
<p>
<a name="honeywell-interop">
<li> FTP to Honeywell site - RASSP Performance Model Interoperability Package <img align="bottom" src="/graphics/rassp-dev.gif">
<ul>
<li><b>Description :</b> This contains RASSP performance model interoperability token <a href= "ftp://ftp.htc.honeywell.com/pub/vhdl/token_std-p.vhdl">package header</a> and <a href="ftp://ftp.htc.honeywell.com/pub/vhdl/token_std-b.vhdl">body</a>.
This package is described in the <A HREF="other/PMIG_V2_0.pdf">VHDL Performance Modeling Interoperability Guideline</A>.
<li>General Taxonomy Level : Performance
<li>Created by : Honeywell Technology Center
</ul>
<p>
<li><A HREF="http://www.c-lab.de/~wolfgang/VHDL/models/coelho.bib/">Code from the Coelho Book</A> - a compressed tar file
<ul>
<li><b> Description :</b>
<li>General Taxonomy Level : Behavioral
<li>Created by : Mani Srivastava (mbs@zion.berkeley.edu),
<li>Wendell Baker (wbaker@ic.berkeley.edu
</ul>
<p>
<li><A HREF="other/fpa.tar.gz">Floating Point Adder Support Package</A> - a compressed tar file <img align="bottom" src="/graphics/rassp-dev.gif">
<ul>
<li><b> Description :</b> Floating Point Adder Type Conversion Support Package
<li>General Taxonomy Level : Behavioral
<li>Created by : Joanne DeGroat, Ohio State University
</ul>
<p>
<li><A HREF="http://www.c-lab.de/~wolfgang/VHDL/models/tlc/">Traffic Light Controller Benchmark</A> - a compressed tar file
<ul>
<li> <b>Description :</b> Benchmark code for the traffic light controller
<li> General Taxonomy Level : RTL
<li> Created by : Champaka Ramachandran, Univ. of Calif., Irvine
<li> champaka@balboa.eng.uci.edu
</ul>
<p>
<li> <A HREF="other/errinj.tar.gz">Error Injector Model and its testbench</A> - a gzipped tar file
<ul>
<li> <b>Description :</b> This component effectively emulates a stuck at
<li> fault, thus emulating an open pin, a short to Vcc, or ground.
<li> General Taxonomy Level : Behavioral
<li> Created by : Ben Cohen, VhdlCohen@aol.com -- Copyright (c) 1995, Ben Cohen. All rights reserved.
</ul>
<p>
<a name="dde-benchmarks">
<li> <A HREF=" http://www.c-lab.de/~wolfgang/VHDL/models/uceng.uc.edu/dde-benchmarks.tar.Z">Benchmarks for High-Level Synthesis</A> - a compressed tar file
<ul>
<li><b>Description :</b> Benchmarks for High-Level Synthesis
<li> Some of the VHDL files contained withing the suite include:
<li> 1) blackjack program, 2) FM8501, a 16-bit microprocessor,
<li> 3) noise generator, 4) decoder for error correction subsystem,
<li> 5) FRISC, a RISC based microprocessor, 6) Functions/Procedures
<li> needed for simulating the Benchmarks, 7) differential equation solver
<li> 8) Intel's I8251 serial IO chip, 9) Texas Instrument's TMS-1000,
<li> 10) Elevator Controller 11) Motorola's 68000, 12) Elliptic Wave
<li> Filter, 13) Mark1 machine, 14) VIPER micro-processor,
<li> 15) encoder for error correction subsystem, 16) Move Machine
<li>General Taxonomy Level : Behavioral
<li> Created by : Ranga Vemuri, P. Mamtora, and J. Roy :
Digital Design Environments, Electrical and Computer Engg, University of Cincinnati, June 1991
</ul>
<p>
<li> <a href="http://www.c-lab.de/~wolfgang/VHDL/models/ISCAS/">Benchmarks for VHDL Simulation</a>
<ul>
<li> <b>Description :</b> Benchmarks for VHDL Simulation:
<li> ISCAS85/ISCAS89 Translation
<li> General Taxonomy Level : Behavioral
<li> Created by : ISCAS
</ul>
<p>
<li> <A HREF="other/validation_tar.gz">VHDL 1076 Validation Test Suite</A> - a compressed tar file
<ul>
<li> <b>Description :</b> DoD/Intermetrics 1076 VDHL Shared Test Suite
<li> General Taxonomy Level : General
<li> Created by : DoD/Intermetrics
<li> Contact : Steve Grout, grout@mcc.com
</ul>
<p>
<li> <A HREF="other/Analog_lib_vhdl.tar.gz">Analog VHDL package</A> - a compressed tar file
<ul>
<li><b> Description :</b> This file contains all necessary VHDL code for running the examples described in chapter 3 of the report "Analog and Mixed Analog-Digital Design Using VHDL".
<li> General Taxonomy Level : Behavioral
<li> Created by : Sveriges Mekanfoerbund and Bernt Arbegard
<li> Email : bernt.arbegard@rsa.ericsson.se
</ul>
<p>
<li> <A HREF="http://www.cdrom.com/pub/languages/vhdl/petri/">Marked Petri Net Package</A> - a compressed tar file
<ul>
<li> <b>Description :</b> This contains a package, package body, and two design entities (with corresponding architectures) to support the construction and evaluation of marked petri nets.
<li> General Taxonomy Level : Behavioral
<li> Created by : Sidhartha Mohanty, Philip a. Wilsey
<li> Email : smohanty@thor.ece.uc.edu, phil.wilsey@uc.edu
</ul>
<p>
<li> <A HREF="http://www.cdrom.com/pub/languages/vhdl/queue/">Queue Modeling Package</A> - a compressed tar file
<ul>
<li> <b>Description :</b> This site contains the tar file of a package, package body, and design entities (with corresponding architectures) to support the construction and evaluation of Queues.
<li> General Taxonomy Level : Behavioral
<li> Created by : Sidhartha Mohanty
<li> Email : smohanty@thor.ece.uc.edu
</ul>
<p>
<li> <A HREF="http://www.informatik.uni-stuttgart.de/ifi/ps/AdaBasis/pal_1195/vhdl/analog/">Mixed-signal circuit-level simulator in VHDL</A>
<ul>
<li> <b>Description :</b> This contains source, documentation, and examples files for the AnaVHDL mixed-signal circuit-level simulator. The entire simulator is written in VHDL.
<li> General Taxonomy Level : Behavioral
<li> Created by : Wenying Zhou, Subramanyam Bangalore
<li> University of Cincinnati, 1993
</ul>
<p>
<li> FTP to VHDl.ORG site <a href="ftp://www.vhdl.org/pub/fmf/fmf_public_models/packages/">Utilities Package for String manipulation and Conversion Routines</a>
<ul>
<li><b> Description :</b> This contains utilities for use with strings and general purpose conversion
<li> General Taxonomy Level : Behavioral
<li> Created by : Jerry A Myers
</ul>
<p>
<li> MsState WWW site - <a href="http://WWW.ERC.MsState.Edu/mpl/vhdl/html/models/library/utilities.html">Utility Packages from Mississippi State</a><img align="bottom" src="/graphics/rassp-dev.gif">
<ul>
<li><b>Description :</b> This contains utilities for the following uses:
<ol>
<li>Jedec file reader: package header and body
<li>Memory paging function with dynamic allocation: package header and body
<li>Memory read/write/init functions: package header and body
<li>Standard Utilities Package header and body
<li>Standard Logic 1164 Utilities Package header and body
</ol> General Taxonomy Level : Behavioral
<li> Created by : Mississippi State University
</ul>
<p>
<li> <A HREF="other/OUTPUT_tar.gz">Data Sources</A> (Updated 5/28/96) - a cpmpressed tar file
<ul>
<li><b>Description :</b> Entity/Architecture for Loading Data from a File and Sourcing Various Formats
<li> General Taxonomy Level : Behavioral
<li> Created by : Tom Rust and Don Day (RGB Spectrum)
<li> Email: tom@rgb.com, don@rgb.com
</ul>
</ul>
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