entity alu_1 is port( opcode_2_port, opcode_1_port, opcode_0_port, a, b, cin, clock : in BIT ; s, cout : out BIT); end alu_1; architecture STRUCTURAL_VIEW of alu_1 is component X_SELECT_OP_9_1_9_1_1 port( DATA1_0_port, DATA2_0_port, DATA3_0_port, DATA4_0_port, DATA5_0_port, DATA6_0_port, DATA7_0_port, DATA8_0_port, DATA9_0_port, CONTROL1_0_port, CONTROL2_0_port, CONTROL3_0_port, CONTROL4_0_port, CONTROL5_0_port, CONTROL6_0_port, CONTROL7_0_port, CONTROL8_0_port, CONTROL9_0_port : in BIT; Z_0_port : out BIT); end component; component X_SELECT_OP_8_1_8_1_1 port( DATA1_0_port, DATA2_0_port, DATA3_0_port, DATA4_0_port, DATA5_0_port, DATA6_0_port, DATA7_0_port, DATA8_0_port, CONTROL1_0_port, CONTROL2_0_port, CONTROL3_0_port, CONTROL4_0_port, CONTROL5_0_port, CONTROL6_0_port, CONTROL7_0_port, CONTROL8_0_port : in BIT; Z_0_port : out BIT); end component; component X_SELECT_OP_4_1_4_1_1 port( DATA1_0_port, DATA2_0_port, DATA3_0_port, DATA4_0_port, CONTROL1_0_port, CONTROL2_0_port, CONTROL3_0_port, CONTROL4_0_port : in BIT; Z_0_port : out BIT); end component; component SYNOP_BASIC_FF port( next_state, clocked_on, force_00, force_01, force_10, force_11 : in BIT; Q, QN : out BIT); end component; signal cout80, cout72, cout74, cout78, cout35, cout39, n91, n94, n84, n85 , n87, n89, n40, n33, n20, n21, n22, n10, n23, n24, n11, n25, n12, n26, n13, n14, n27, n15, n16, n17, n18, n19, s_port, cout_port, n1, n4, n5, n6 , s63, n7, n8, s65, n9, s67, s55, s57, s32, s59, Logic0, Logic1, s28 : BIT; begin s <= s_port; cout <= cout_port; n11 <= (n1 and n10); n13 <= (n1 and n12); n15 <= (n1 and n14); cout_reg : SYNOP_BASIC_FF port map( next_state => cout35, clocked_on => clock, force_00 => Logic0, force_01 => Logic0, force_10 => Logic0, force_11 => Logic0, Q => cout_port, QN => open); s_reg : SYNOP_BASIC_FF port map( next_state => s28, clocked_on => clock, force_00 => Logic0, force_01 => Logic0, force_10 => Logic0, force_11 => Logic0, Q => s_port, QN => open ); Logic0 <= '0'; Logic1 <= '1'; n89 <= (a xor b); cout78 <= ((a and cin) or (b and n91)); n91 <= (a xor cin); s63 <= (a xor b); U30 : X_SELECT_OP_9_1_9_1_1 port map( DATA1_0_port => Logic1, DATA2_0_port => Logic1, DATA3_0_port => Logic1, DATA4_0_port => Logic1, DATA5_0_port => Logic1, DATA6_0_port => Logic1, DATA7_0_port => Logic1, DATA8_0_port => Logic1, DATA9_0_port => Logic0, CONTROL1_0_port => n5, CONTROL2_0_port => n7, CONTROL3_0_port => n9, CONTROL4_0_port => n11, CONTROL5_0_port => n13, CONTROL6_0_port => n15, CONTROL7_0_port => n17, CONTROL8_0_port => n19, CONTROL9_0_port => n27, Z_0_port => n33); s59 <= not(n94); U31 : X_SELECT_OP_8_1_8_1_1 port map( DATA1_0_port => Logic0, DATA2_0_port => s55, DATA3_0_port => s57, DATA4_0_port => s59, DATA5_0_port => b, DATA6_0_port => s63, DATA7_0_port => s65, DATA8_0_port => s67, CONTROL1_0_port => n5, CONTROL2_0_port => n7, CONTROL3_0_port => n9, CONTROL4_0_port => n11, CONTROL5_0_port => n13, CONTROL6_0_port => n15, CONTROL7_0_port => n17, CONTROL8_0_port => n19, Z_0_port => s32); n94 <= (a xor cin); U32 : X_SELECT_OP_9_1_9_1_1 port map( DATA1_0_port => Logic0, DATA2_0_port => Logic0, DATA3_0_port => Logic1, DATA4_0_port => Logic1, DATA5_0_port => Logic0, DATA6_0_port => Logic0, DATA7_0_port => Logic1, DATA8_0_port => Logic1, DATA9_0_port => Logic0, CONTROL1_0_port => n5, CONTROL2_0_port => n7, CONTROL3_0_port => n9, CONTROL4_0_port => n11, CONTROL5_0_port => n13, CONTROL6_0_port => n15, CONTROL7_0_port => n17, CONTROL8_0_port => n19, CONTROL9_0_port => n27, Z_0_port => n40); s28 <= ((s_port and not(n33)) or (s32 and n33)); cout74 <= (not(a) and cin); U33 : X_SELECT_OP_4_1_4_1_1 port map( DATA1_0_port => cout72, DATA2_0_port => cout74, DATA3_0_port => cout78, DATA4_0_port => cout80, CONTROL1_0_port => n9, CONTROL2_0_port => n11, CONTROL3_0_port => n17, CONTROL4_0_port => n19, Z_0_port => cout39); s57 <= (a xor cin); cout35 <= ((cout_port and not(n40)) or (cout39 and n40)); s67 <= (n84 xor cin); n4 <= (not((opcode_2_port xor '0')) and not((opcode_1_port xor '0')) and not((opcode_0_port xor '0'))); n84 <= (a xor n85); cout72 <= (a and cin); n6 <= (not((opcode_2_port xor '0')) and not((opcode_1_port xor '0')) and not((opcode_0_port xor '1'))); n85 <= not(b); n17 <= (n1 and n16); s55 <= not(a); n19 <= (n1 and n18); n8 <= (not((opcode_2_port xor '0')) and not((opcode_1_port xor '1')) and not((opcode_0_port xor '0'))); cout80 <= ((a and cin) or (not(b) and n87)); n87 <= (a xor cin); n10 <= (not((opcode_2_port xor '0')) and not((opcode_1_port xor '1')) and not((opcode_0_port xor '1'))); n20 <= (n1 and not(n4)); s65 <= (n89 xor cin); n21 <= (n20 and not(n6)); n12 <= (not((opcode_2_port xor '1')) and not((opcode_1_port xor '0')) and not((opcode_0_port xor '0'))); n14 <= (not((opcode_2_port xor '1')) and not((opcode_1_port xor '0')) and not((opcode_0_port xor '1'))); n22 <= (n21 and not(n8)); n23 <= (n22 and not(n10)); n16 <= (not((opcode_2_port xor '1')) and not((opcode_1_port xor '1')) and not((opcode_0_port xor '0'))); n24 <= (n23 and not(n12)); n18 <= (not((opcode_2_port xor '1')) and not((opcode_1_port xor '1')) and not((opcode_0_port xor '1'))); n25 <= (n24 and not(n14)); n26 <= (n25 and not(n16)); n27 <= (n26 and not(n18)); n1 <= '1'; n5 <= (n1 and n4); n7 <= (n1 and n6); n9 <= (n1 and n8); end STRUCTURAL_VIEW; -- This is the basic technology-independent flip-flop. -- All flip-flops and latches are written in terms of this. entity SYNOP_BASIC_FF is port(next_state, clocked_on, force_00, force_01, force_10, force_11: in BIT; Q, QN: out BIT); end SYNOP_BASIC_FF ; architecture RTL of SYNOP_BASIC_FF is signal t_q: BIT ; begin process ( force_00, force_01, force_10, force_11, clocked_on ) begin if ( force_00 = '1' or force_01 = '1' ) then t_q <= '0' ; elsif ( force_10 = '1' or force_11 = '1' ) then t_q <= '1' ; elsif ( clocked_on'event and clocked_on = '1' ) then t_q <= next_state ; end if ; end process ; process ( t_q, force_00, force_11 ) begin Q <= t_q ; if ( force_00 = '1' or force_11 = '1' ) then QN <= t_q ; else QN <= not t_q ; end if ; end process ; end RTL ;