------------------------------------------------------------------------------- -- EE126 Project #1, part I Testbench -- by: Frank Bruno ------------------------------------------------------------------------------- ENTITY test_mult IS END test_mult; ARCHITECTURE b_mult OF test_mult IS COMPONENT mult PORT(multiplier : IN bit_vector(3 DOWNTO 0); multiplicand : IN bit_vector(3 DOWNTO 0); clock : IN bit; init : IN bit; ac : BUFFER bit_vector(3 DOWNTO 0); qout : BUFFER bit_vector(3 DOWNTO 0); sc : BUFFER integer range 0 to 4; qr : BUFFER bit_vector(4 DOWNTO 0); br : BUFFER bit_vector(3 DOWNTO 0); done : OUT bit); END COMPONENT; SIGNAL multiplier : bit_vector(3 DOWNTO 0); SIGNAL multiplicand : bit_vector(3 DOWNTO 0); SIGNAL clock : bit; SIGNAL init : bit; SIGNAL ac : bit_vector(3 DOWNTO 0); SIGNAL qout : bit_vector(3 DOWNTO 0); SIGNAL done : bit; SIGNAL sc : integer range 0 to 4; SIGNAL qr : bit_vector(4 DOWNTO 0); SIGNAL br : bit_vector(3 DOWNTO 0); BEGIN -- b_mult u1: mult PORT MAP(multiplier => multiplier, multiplicand => multiplicand, clock => clock, init => init, ac => ac, qout => qout, sc => sc, qr => qr, br => br, done => done); clock_gen: PROCESS BEGIN clock <= '0' AFTER 40 ns; WAIT FOR 40 ns; clock <= '1' AFTER 40 ns; WAIT FOR 40 ns; END PROCESS; PROCESS VARIABLE state : integer := 0; BEGIN WAIT UNTIL clock'EVENT AND clock ='1'; CASE state IS WHEN 0 => init <= '0'; multiplier <= "1011"; multiplicand <= "1001"; state := 1; WHEN 1 => init <= '1'; IF (done = '1') THEN init <= '0'; multiplier <= "0111"; multiplicand <= "0101"; state := 2; END IF; WHEN 2 => init <= '1'; state := 3; WHEN 3 => IF (done = '1') THEN init <= '0'; multiplier <= "1011"; multiplicand <= "0110"; state := 4; END IF; WHEN 4 => init <= '1'; state := 5; WHEN OTHERS => END CASE; END PROCESS; END b_mult; CONFIGURATION c_mult OF test_mult IS FOR b_mult FOR u1: mult USE ENTITY work.mult; END FOR; END FOR; END c_mult;