------------------------------------------------------------------------------- -- Simple processor from EE126 -- By: Frank Bruno -- for Professor Chang ------------------------------------------------------------------------------- USE work.alu_pkg.ALL; USE work.bv_arithmetic.ALL; ENTITY processor_test IS END processor_test; ARCHITECTURE process_test OF processor_test IS COMPONENT processor PORT(carry : BUFFER bit; out_reg : BUFFER bit_vector(3 DOWNTO 0); pc_out : BUFFER bit_vector(3 DOWNTO 0); input : IN bit_vector(3 DOWNTO 0); clock : IN bit; reset : IN bit; inc_pc : IN bit; instr : IN bit_vector(7 DOWNTO 0); load : IN bit; start : IN bit ); END COMPONENT; SIGNAL carry : bit; SIGNAL out_reg : bit_vector(3 DOWNTO 0); SIGNAL pc_out : bit_vector(3 DOWNTO 0); SIGNAL input : bit_vector(3 DOWNTO 0); SIGNAL clock : bit; SIGNAL reset : bit; SIGNAL inc_pc : bit; SIGNAL instr : bit_vector(7 DOWNTO 0); SIGNAL load : bit; SIGNAL start : bit; BEGIN -- process_test u1: processor PORT MAP(carry => carry, out_reg => out_reg, pc_out => pc_out, input => input, clock => clock, reset => reset, inc_pc => inc_pc, instr => instr, load => load, start => start); clock_gen: PROCESS BEGIN clock <= '0' AFTER 40 ns; WAIT FOR 40 ns; clock <= '1' AFTER 40 ns; WAIT FOR 40 ns; END PROCESS; PROCESS VARIABLE t_state : integer := 0; BEGIN WAIT until clock'event and clock = '1'; CASE t_state IS WHEN 0 => -- set up for a load reset <= '1'; inc_pc <= '0'; load <= '0'; start <= '0'; WHEN 1 => -- start loading reset <= '0'; load <= '1'; inc_pc <= '1'; instr <= "11001101"; WHEN 2 => instr <= "10010000"; WHEN 3 => instr <= "10000100"; WHEN 4 => instr <= "11001001"; WHEN 5 => instr <= "10011010"; WHEN 6 => instr <= "10011111"; WHEN 7 => instr <= "00010000"; WHEN 8 => instr <= "11101011"; WHEN 9 => instr <= "01000110"; WHEN 10 => instr <= "00101111"; WHEN 11 => instr <= "11010110"; WHEN 12 => instr <= "11000111"; WHEN 13 => instr <= "11000110"; WHEN 14 => instr <= "11010000"; WHEN 15 => load <= '0'; inc_pc <= '0'; reset <= '1'; WHEN 16 => reset <= '0'; WHEN 17 => -- begin start <= '1'; input <= "0010"; WHEN 18 => start <= '0'; WHEN 23 => start <= '1'; input <= "0111"; WHEN 24 => start <= '0'; WHEN 220 => start <= '1'; WHEN others => start <= '0'; END CASE; -- state t_state := t_state + 1; END PROCESS; END process_test; CONFIGURATION process_test_config OF processor_test IS FOR process_test FOR u1: processor USE ENTITY work.processor; END FOR; -- END FOR; -- END process_test_config;