LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.mem_pack_con.ALL;
USE WORK.synthesis_utilities.ALL;
USE WORK.global_environment.ALL;
USE WORK.alu_operations.ALL;  
USE WORK.PackCon.ALL;

--
ENTITY arithmetic_logic_unit IS
  PORT (code : IN std_logic_vector (2 DOWNTO 0); alu_operate : IN std_logic);
END arithmetic_logic_unit;
--
ARCHITECTURE Concurrent OF arithmetic_logic_unit IS
BEGIN
  coding: PROCESS (alu_operate)
  BEGIN
  -- free
    DeAlloc(alu_out);  
    DeAlloc(alu_flags);
    
    CASE code IS
      WHEN a_add_b | a_sub_b => 
        AddSub(code(1), ac_out, dbus, alu_out, sr_out, alu_flags); 
      WHEN a_and_b =>        
        AndSetflags(ac_out, dbus, alu_out, sr_out, alu_flags);
      WHEN a_input  =>         
        EquateSetFlags(dbus, alu_out, sr_out, alu_flags);
      WHEN b_input  =>
        EquateSetFlags(ac_out, alu_out, sr_out, alu_flags);
      WHEN b_compl =>
        NotSetFlags(ac_out, alu_out, sr_out, alu_flags);
      WHEN OTHERS => 
        alu_out := zero_8;
        alu_flags := zero_4;
    END CASE;

  END PROCESS coding;
END Concurrent;