--	Model Name	: Concurrent - Memory Address Register 

--	Author		: Armita Peymandoust 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.




LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.synthesis_utilities.ALL;
USE WORK.synthesis_parameters.ALL;
USE WORK.global_environment.ALL;
USE WORK.PackCon.ALL; 

--
ENTITY memory_address_register_unit IS
  PORT (load_page, load_offset : IN std_logic);
END memory_address_register_unit;
--
ARCHITECTURE Concurrent OF memory_address_register_unit IS
BEGIN

  p1: PROCESS (load_page)
  BEGIN
              -- first free
    DeAlloc(mar_page_out);
     
              -- allocate for the new data
    Equate(mar_page_bus, mar_page_out); 
        
  END PROCESS p1;

  p2: PROCESS (load_offset)
  BEGIN
              -- first free
    DeAlloc(mar_offset_out);
    
              -- allocate for the new data
    Equate(mar_offset_bus, mar_offset_out);
    
  END PROCESS p2;

END Concurrent;