LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.synthesis_utilities.ALL;
USE WORK.synthesis_parameters.ALL;
USE WORK.global_environment.ALL;
--
--
ENTITY par_central_processing_unit IS
  PORT (interrupt : IN std_logic;
        read_mem, write_mem : OUT std_logic
       );
END par_central_processing_unit;
--
ARCHITECTURE Concurrent OF par_central_processing_unit IS
  --
  COMPONENT par_data_path 
  PORT (load_ac, zero_ac, 
        load_ir, 
        increment_pc, load_page_pc, load_offset_pc, reset_pc,
        load_page_mar, load_offset_mar, 
        load_sr, cm_carry_sr, 
        pc_on_mar_page_bus, ir_on_mar_page_bus, 
        pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
        pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
        mar_on_adbus,
        dbus_on_databus,
        arith_shift_left, arith_shift_right, no_shift,
        alu_operate : IN std_logic;
        alu_code : IN std_logic_vector (2 DOWNTO 0)
       );
  END COMPONENT; 
  FOR data: par_data_path USE ENTITY WORK.par_data_path(Concurrent);
  --
  COMPONENT par_control_unit
  PORT (load_ac, zero_ac, 
        load_ir, 
        increment_pc, load_page_pc, load_offset_pc, reset_pc,
        load_page_mar, load_offset_mar, 
        load_sr, cm_carry_sr, 
        pc_on_mar_page_bus, ir_on_mar_page_bus, 
        pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
        pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
        mar_on_adbus,
        dbus_on_databus,
        arith_shift_left, arith_shift_right, no_shift,
        alu_operate : OUT std_logic;
        alu_code : OUT std_logic_vector (2 DOWNTO 0);
        read_mem, write_mem : OUT std_logic; interrupt : IN std_logic
       );
  END COMPONENT; 
  FOR ctrl: par_control_unit USE ENTITY WORK.par_control_unit(Concurrent);
  --
  SIGNAL load_ac, zero_ac, 
         load_ir, 
         increment_pc, load_page_pc, load_offset_pc, reset_pc,
         load_page_mar, load_offset_mar, 
         load_sr, cm_carry_sr, 
         pc_on_mar_page_bus, ir_on_mar_page_bus, 
         pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
         pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
         mar_on_adbus,
         dbus_on_databus,
         arith_shift_left, arith_shift_right, no_shift,
         alu_operate : std_logic;
  SIGNAL alu_code : std_logic_vector (2 DOWNTO 0);
  SIGNAL ir_lines : byte; 
  SIGNAL status : nibble;
BEGIN
  data: par_data_path PORT MAP
        (load_ac, zero_ac, 
         load_ir, 
         increment_pc, load_page_pc, load_offset_pc, reset_pc,
         load_page_mar, load_offset_mar, 
         load_sr, cm_carry_sr, 
         pc_on_mar_page_bus, ir_on_mar_page_bus, 
         pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
         pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
         mar_on_adbus,
         dbus_on_databus, 
         arith_shift_left, arith_shift_right, no_shift,
         alu_operate,
         alu_code
        );
  ctrl: par_control_unit PORT MAP 
        (load_ac, zero_ac, 
         load_ir, 
         increment_pc, load_page_pc, load_offset_pc, reset_pc,
         load_page_mar, load_offset_mar, 
         load_sr, cm_carry_sr, 
         pc_on_mar_page_bus, ir_on_mar_page_bus, 
         pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
         pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
         mar_on_adbus,
         dbus_on_databus, 
         arith_shift_left, arith_shift_right, no_shift,
         alu_operate,
         alu_code,
         read_mem, write_mem, interrupt
        );
END Concurrent;