LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.synthesis_utilities.ALL;
USE WORK.synthesis_parameters.ALL;
USE WORK.global_environment.ALL;
USE WORK.PackCon.ALL;

--
ENTITY status_register_unit IS
  PORT (load, cm_carry : IN std_logic );
END status_register_unit;
--
ARCHITECTURE Concurrent OF status_register_unit IS
BEGIN
  PROCESS (load, cm_carry)
    VARIABLE temp : nibble_node_ptr :=NULL;
  BEGIN
    IF load'EVENT THEN
                -- first free
      DeAlloc(sr_out);
       
                -- allocate for the new data
      Equate(shu_flags, sr_out);
      
    ELSE
      IF sr_out = zero_4 THEN 
        sr_out := NEW nibble_node;
        sr_out.val:="0000"; 
      END IF;
      temp := sr_out;
      WHILE temp/=NULL LOOP
        temp.val (2) := NOT temp.val (2);
        temp := temp.link;
      END LOOP;
    END IF;
  END PROCESS;
END Concurrent;