--	Model Name	: Parwan Memory Address Register 

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.synthesis_parameters.ALL;
USE WORK.synthesis_utilities.ALL;
USE WORK.global_environment.ALL;
--
ENTITY memory_address_register_unit IS
PORT (load_page, load_offset : IN std_logic);
END memory_address_register_unit;
--
ARCHITECTURE synthesizable_behavioral OF memory_address_register_unit IS
BEGIN
    p1: PROCESS (load_page)
    BEGIN
      mar_out (11 DOWNTO 8) := mar_bus (11 DOWNTO 8);
    END PROCESS p1;

    p2: PROCESS (load_offset)
    BEGIN

      mar_out (7 DOWNTO 0) := mar_bus (7 DOWNTO 0);
    END PROCESS p2;
END synthesizable_behavioral;