-- Model Name : Parwan Tester
-- Author : Zainalabedin Navabi
-- Last Updated : 09 / 15 / 1996
-- This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
USE EXEMPLAR.exemplar.ALL;
--
LIBRARY WORK;
USE WORK.ALL;
USE WORK.synthesis_parameters.ALL;
USE WORK.synthesis_utilities.ALL;
USE WORK.global_environment.ALL;
--
ENTITY parwan_tester IS
END parwan_tester;
--
ARCHITECTURE input_output OF parwan_tester IS
COMPONENT parwan
PORT (interrupt : IN std_logic; read_mem, write_mem : OUT std_logic;
halted : OUT std_logic := '0'; ready : IN std_logic
);
END COMPONENT;
FOR cpu : parwan USE ENTITY WORK.par_central_processing_unit(dataflow_synthesizable);
COMPONENT parmem PORT (cs, rwbar : IN std_logic); END COMPONENT;
FOR mem : parmem USE ENTITY WORK.parwan_memory (behavioral);
SIGNAL clock, interrupt, read, write : std_logic := '0';
SIGNAL data : byte;
SIGNAL address : twelve;
SIGNAL cs, halted, ready : std_logic := '0';
CONSTANT duty : TIME := 2 US;
CONSTANT period : TIME := duty * 2;
CONSTANT wait_state : INTEGER := 0;
BEGIN
clk : clock <= NOT clock AFTER duty WHEN halted='0' ELSE clock;
int : interrupt <= '1', '0' AFTER 4500 NS;
ck2 : cck <= clock;
cs <= read OR write;
wait_cycle: PROCESS
BEGIN
IF clock = '0' THEN
WAIT FOR 20 NS;
IF cs = '1' THEN
WAIT FOR period * wait_state;
ready <= '1', '0' AFTER period;
END IF;
END IF;
WAIT ON clock;
END PROCESS wait_cycle;
PROCESS (clock) BEGIN data <= databus; address <= adbus; END PROCESS;
cpu : parwan PORT MAP (interrupt, read, write, halted, '1');--ready);
mem : parmem PORT MAP (cs => cs, rwbar => read);
-- dump_signal <= '1' WHEN halt='1';
END input_output;