-- Model Name : Reduced Activity - Parwan Shifter
-- Author : Zainalabedin Navabi
-- Last Updated : 09 / 15 / 1996
-- This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.synthesis_parameters.ALL;
USE WORK.synthesis_utilities.ALL;
USE WORK.global_environment.ALL;
--
ENTITY shifter_unit IS
PORT (arith_shift_left, arith_shift_right, no_shift : IN std_logic);
END shifter_unit;
--
ARCHITECTURE synthesizable_behavioral OF shifter_unit IS
BEGIN
coding: PROCESS (arith_shift_left, arith_shift_right, no_shift)
VARIABLE t : std_logic_vector (7 DOWNTO 0);
VARIABLE v, c, z, n : std_logic; --in_flags 3210
BEGIN
IF arith_shift_left'EVENT THEN
t := alu_out (6 DOWNTO 0) & '0';
n := t (7);
z := NOT all_or (t);
c := alu_out (7);
v := alu_out (6) XOR alu_out (7);
ELSIF arith_shift_right'EVENT THEN
t := alu_out (7) & alu_out (7 DOWNTO 1);
n := t (7);
z := NOT all_or (t);
c := alu_flags(2);
v := alu_flags(3);
ELSE -- none are '1'
t := alu_out (7 DOWNTO 0);
n := alu_flags(0);
z := alu_flags(1);
c := alu_flags(2);
v := alu_flags(3);
END IF;
obus := t;
shu_flags := v & c & z & n;
END PROCESS coding;
END synthesizable_behavioral;