VHDL Analyzer - V5.2; Powerview 5.2 (051494)
c Copyright 1985,1994 by Viewlogic Systems, Inc.
Analyzing lfsr.vhd; Making lfsr.vsm lfsr.vli lfsr.lis.
1: ---------------------------------------------------------------
2: -- L F S R . V
3: -- Scott Harrington
4: -- Spring 1995
5: -- VHDL source for simple GERM LFSR counter
6: --
7: -- For 3, 4, 6, 7, or 15 bit LFSR the XNOR feedback is from
8: -- the two most significant output bits.
9: -- See Xilinx Data Book p. 9-24.
10: ----------------------------------------------------------------
11:
12: LIBRARY IEEE;
13: USE IEEE.std_logic_1164.ALL;
14:
15: -----------------------
16: -- I/O descriptions: --
17: -----------------------
18:
19: -- Clk: FPGA TCLK
20: -- CE: Clock Enable to LFSR flip flops
21: -- CLR: Synchronous CLR to all zeros
22: -- Q3-0: output bits, pseudorandom sequence of length 15
23: -- (BUFFER type allows Q's value to be read as well as written)
24:
25: ENTITY lfsr IS
***** FAILURE: 24, can't find input file std_logic_1164.vhd
1 error; 0 warnings; 0 extensions; 0 notes.
VHDL Analysis of lfsr.vhd completed.
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