Verilog Quick Reference

For the sake of brevity throughout the following examples, names are sometimes used without being declared.

Syntax Reference

module M (P1, P2, P3, P4);
  input P1, P2;
  output [7:0] P3;
  inout P4;

  reg ...
  wire ...
  parameter ...

  initial
  begin
    // Statements
  end

  always @(...)
  begin
    // Statements
  end

  // Continuous assignments...
  assign W1 = Expression;

  // Module instances...
  COMP U1 (S1, S2);
  COMP U2 (.P1(S1), .P2(S2));

  task T1;
    input A1;
    inout A2;
    output A3;
  begin
    // Statements
  end
  endtask

  function [7:0] F1;
    input A1;
  begin
    // Statements
    F1 = Expression;
  end
  endfunction

endmodule
Statements
Reg = Expression;
Reg <= Expression;
TaskEnable(...);
#delay
wait (Expression)
@(a or b or c)
@(posedge clk)

if (Condition)
  ...
else if (Condition)
  ...
else
  ...

case (Selection)
  Choice1 :
  ...
  Choice2, Choice3 :
  ...
  default :
  ...
endcase

for (I=0; I<MAX; I=I+1)
  ...
repeat (8)
  ...
while (Condition)
  ...
forever
  ...

Reserved Words

and             for           output       strong1
always          force         parameter    supply0
assign          forever       pmos         supply1
begin           fork          posedge      table
buf             function      primitive    task
bufif0          highz0        pulldown     tran
bufif1          highz1        pullup       tranif0
case            if            pull0        tranif1
casex           ifnone        pull1        time
casez           initial       rcmos        tri
cmos            inout         real         triand
deassign        input         realtime     trior
default         integer       reg          trireg
defparam        join          release      tri0
disable         large         repeat       tri1
edge            macromodule   rnmos        vectored
else            medium        rpmos        wait
end             module        rtran        wand
endcase         nand          rtranif0     weak0
endfunction     negedge       rtranif1     weak1
endprimitive    nor           scalared     while
endmodule       not           small        wire
endspecify      notif0        specify      wor
endtable        notif1        specparam    xnor
endtask         nmos          strength     xor
event           or            strong0

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