--
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky, Puneet Mehra
-- 12/30/98
-- Version 1.2
-- Notes: This file implements the CODEC device. This device compress
-- or decompress the data
--
-- The CODEC has three 32 bit registers: the input register to put
-- the data that to be compress or decompress, the output register
-- that stores the compressed or decompressed data, and control/
-- status registers.
--
-- IN_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- | NU .......................................... NU | B/W |
-- ---------------------------------------------------------------
-- 8-bits
-- OUT_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- | NU .......................................... NU | B/W |
-- ---------------------------------------------------------------
-- 8-bits
--
-- STAT_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- |NU................................................... NU|READY |
-- ---------------------------------------------------------------
-- ^
-- |
-- |
-- |
-- set = data is ready----------------------------------------
--
--
--
-- CONT_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- |NU...........................................NU|COMPRESS |START|
-- ---------------------------------------------------------------
-- ^ ^
-- | |
-- | |
-- set to compress and reset to decompress ------------ |
-- set to start the operation --------------------------------
--
--*************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--*************************************************************************--
entity CODEC_IN is
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027;
COMPRESSION : INTEGER:=1);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : in UNSIGNED(22 downto 0);
ib_wr : in STD_LOGIC;
ib_rd : in STD_LOGIC;
ib_valid : out STD_LOGIC );
end CODEC_IN;
--*************************************************************************--
architecture BHV_CODEC_IN of CODEC_IN is
--
-- type declarations
--
type STATE_TYPE is (IDLE,COMP,DECOMP,DONE);
--
-- constant declarations
--
constant Z_32 : UNSIGNED(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant Z_23 : UNSIGNED(22 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZ";
constant C0_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000000";
constant C1_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000001";
--
-- type declarations
--
subtype REG_CELL is UNSIGNED(31 downto 0);
type REG_TYPE is array(COMPRESSION-1 downto 0) of REG_CELL;
--
-- signal declarations
--
signal location: INTEGER range 0 to 4;
signal in_reg : REG_TYPE;
signal out_reg,stat_reg,cont_reg: UNSIGNED(31 downto 0);
signal state : STATE_TYPE;
begin
process(clk, rst)
variable temp, temp2 : INTEGER range 0 to 31;
begin
if( rst = '1' ) then
stat_reg <= C0_32;
out_reg <= C0_32;
state <= IDLE;
elsif( clk'event and clk = '1' ) then
case(state) is
when IDLE =>
if(cont_reg(0)='1' ) then
stat_reg(0) <= '0';
if( cont_reg(1) = '1' ) then
state <= COMP;
else
state <= DECOMP;
end if;
end if;
when COMP =>
for temp in 0 to COMPRESSION-1 loop
temp2 := temp * 8;
out_reg(temp2+7 downto temp2) <= in_reg(temp)(7 downto 0);
end loop;
state <= DONE;
when DECOMP =>
out_reg <= C0_32;
for temp in 0 to COMPRESSION-1 loop
temp2 := temp * 8;
out_reg(temp2+7 downto temp2) <= in_reg(temp)(7 downto 0);
end loop;
state <= DONE;
when DONE =>
stat_reg(0) <= '1';
if( cont_reg(0) = '0' ) then
state <= IDLE;
end if;
end case;
end if;
end process;
--
-- register read/write process
--
process(clk, rst)
begin
if( rst = '1' ) then
--
-- steady state
--
ib_data <= Z_32;
ib_valid <= '0';
cont_reg <= C0_32;
location <= 0;
for i in 0 to (COMPRESSION-1) loop
in_reg(i) <= C0_32;
end loop; -- i
elsif( clk'event and clk = '1' ) then
--
-- steady state
--
ib_data <= Z_32;
ib_valid <= '0';
if( ib_wr = '1' ) then
if( ib_addr =
conv_integer(CONT_REG_ADDR) ) then
cont_reg <= ib_data ;
elsif( ib_addr =
conv_integer(IN_REG_ADDR) ) then
in_reg(location) <= ib_data;
location <= location + 1;
if(location = COMPRESSION-1) then
location <= 0;
end if;
end if;
elsif( ib_rd = '1' ) then
if( ib_addr =
conv_integer(STAT_REG_ADDR) ) then
ib_data <= stat_reg;
ib_valid <= '1';
elsif(ib_addr =
conv_integer(OUT_REG_ADDR)) then
ib_data <= out_reg;
ib_valid <= '1';
end if;
end if;
end if;
end process;
end BHV_CODEC_IN;
--*************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--*************************************************************************--
entity CODEC_IM is
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : out UNSIGNED(22 downto 0);
ib_wr : out STD_LOGIC;
ib_rd : out STD_LOGIC;
ib_valid : in STD_LOGIC;
pdata : inout UNSIGNED(7 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end CODEC_IM;
--*************************************************************************--
architecture BHV_CODEC_IM of CODEC_IM is
--
-- type declarations
--
type STATE_TYPE is (IDLE_S, READ_S, READ_WAIT_S, WRITE_S );
type ISA_STATE_TYPE is (IDLE_ISA_S, READ_WRITE_S, READ1_S,
READ1_WAIT_S,
READ2_IDLE_S, READ2_CHK_S, READ2_S, READ2_WAIT_S,
READ3_IDLE_S, READ3_CHK_S, READ3_S, READ3_WAIT_S,
READ4_IDLE_S, READ4_CHK_S, READ4_S, READ4_WAIT_S,
WRITE1_S, WRITE1_WAIT_S,
WRITE2_IDLE_S, WRITE2_CHK_S, WRITE2_S, WRITE2_WAIT_S,
WRITE3_IDLE_S, WRITE3_CHK_S, WRITE3_S, WRITE3_WAIT_S,
WRITE4_IDLE_S, WRITE4_CHK_S, WRITE4_S, WRITE4_WAIT_S
);
--
-- constant declarations
--
constant Z_32 : UNSIGNED(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant C0_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000000";
constant Z_23 : UNSIGNED(22 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZ";
constant C0_23 : UNSIGNED(22 downto 0) :=
"00000000000000000000000";
constant Z_8 : UNSIGNED(7 downto 0) :=
"ZZZZZZZZ";
--
-- signal declarations
--
signal isa_data, isa_data_read : UNSIGNED (31 downto 0);
signal isa_addr : UNSIGNED(22 downto 0);
signal isa_wr, isa_rd, read_done, write_done : STD_LOGIC;
signal state : STATE_TYPE;
signal isa_state : ISA_STATE_TYPE;
begin
process(clk, rst)
begin
if( rst = '1' ) then
--
-- steady state
--
state <= IDLE_S;
ib_addr <= C0_23;
ib_data <= Z_32;
ib_rd <= '0';
ib_wr <= '0';
isa_data_read <= C0_32;
read_done <= '0';
write_done <= '0';
elsif( clk'event and clk = '1' ) then
--
-- steady state
--
ib_addr <= C0_23;
ib_data <= Z_32;
ib_rd <= '0';
ib_wr <= '0';
read_done <= '0';
write_done <= '0';
case ( state ) is
when IDLE_S =>
if( isa_rd = '1' ) then
ib_addr <= isa_addr;
ib_rd <= '1';
state <= READ_S;
elsif( isa_wr = '1' ) then
ib_data <= isa_data;
ib_addr <= isa_addr;
ib_wr <= '1';
state <= WRITE_S;
end if;
when READ_S =>
state <= READ_WAIT_S;
when READ_WAIT_S =>
if( ib_valid = '1' ) then
isa_data_read <= ib_data;
read_done <= '1';
state <= IDLE_S;
else
state <= READ_WAIT_S;
end if;
when WRITE_S =>
write_done <= '1';
state <= IDLE_S;
when others =>
state <= IDLE_S;
end case;
end if;
end process;
--
-- ISA mux process
--
process(clk, rst)
begin
if( rst = '1') then
--
-- steady state
--
isa_state <= IDLE_ISA_S;
isa_data <= C0_32;
isa_addr <= C0_23;
isa_wr <= '0';
isa_rd <= '0';
iochrdy <= 'Z';
pdata <= Z_8;
elsif( clk'event and clk = '1') then
--
-- steady state
--
isa_wr <= '0';
isa_rd <= '0';
iochrdy <= 'Z';
pdata <= Z_8;
case( isa_state ) is
when IDLE_ISA_S =>
if( ale = '1' ) then
if ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
isa_addr <= paddr;
isa_state <= READ_WRITE_S;
else
isa_state <= IDLE_ISA_S;
end if;
else
isa_state <= IDLE_ISA_S;
end if;
when READ_WRITE_S =>
if( ior = '1' ) then
iochrdy <= '0';
isa_rd <= '1';
isa_state <= READ1_S;
elsif( iow = '1') then
iochrdy <= '0';
isa_addr <= paddr;
isa_data(7 downto 0) <= pdata;
isa_state <= WRITE1_S;
else
isa_state <= IDLE_ISA_S;
end if;
when READ1_S =>
iochrdy <= '0';
isa_state <= READ1_WAIT_S;
when READ1_WAIT_S =>
if( read_done = '1' ) then
iochrdy <= '1';
pdata <= isa_data_read(7 downto 0);
isa_state <= READ2_IDLE_S;
else
iochrdy <= '0';
isa_state <= READ1_WAIT_S;
end if;
when READ2_IDLE_S =>
if( ale = '1' ) then
if( paddr = isa_addr ) then
isa_state <= READ2_CHK_S;
elsif ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
isa_addr <= paddr;
isa_state <= READ_WRITE_S;
else
isa_state <= IDLE_ISA_S;
end if;
else
isa_state <= READ2_IDLE_S;
end if;
when READ2_CHK_S =>
if( ior = '1' ) then
iochrdy <= '0';
isa_state <= READ2_S;
elsif( iow = '1') then
iochrdy <= '0';
isa_addr <= paddr;
isa_data(7 downto 0) <= pdata;
isa_state <= WRITE1_S;
else
isa_state <= IDLE_ISA_S;
end if;
when READ2_S =>
iochrdy <= '0';
isa_state <= READ2_WAIT_S;
when READ2_WAIT_S =>
iochrdy <= '1';
pdata <= isa_data_read(15 downto 8);
isa_state <= READ3_IDLE_S;
when READ3_IDLE_S =>
if( ale = '1' ) then
if( paddr = isa_addr ) then
isa_state <= READ3_CHK_S;
elsif ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
isa_addr <= paddr;
isa_state <= READ_WRITE_S;
else
isa_state <= IDLE_ISA_S;
end if;
else
isa_state <= READ3_IDLE_S;
end if;
when READ3_CHK_S =>
if( ior = '1' ) then
iochrdy <= '0';
isa_state <= READ3_S;
elsif( iow = '1') then
iochrdy <= '0';
isa_addr <= paddr;
isa_data(7 downto 0) <= pdata;
isa_state <= WRITE1_S;
else
isa_state <= IDLE_ISA_S;
end if;
when READ3_S =>
iochrdy <= '0';
isa_state <= READ3_WAIT_S;
when READ3_WAIT_S =>
iochrdy <= '1';
pdata <= isa_data_read(23 downto 16);
isa_state <= READ4_IDLE_S;
when READ4_IDLE_S =>
if( ale = '1' ) then
if( paddr = isa_addr ) then
isa_state <= READ4_CHK_S;
elsif ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
isa_addr <= paddr;
isa_state <= READ_WRITE_S;
else
isa_state <= IDLE_ISA_S;
end if;
else
isa_state <= READ4_IDLE_S;
end if;
when READ4_CHK_S =>
if( ior = '1' ) then
iochrdy <= '0';
isa_state <= READ4_S;
elsif( iow = '1') then
iochrdy <= '0';
isa_addr <= paddr;
isa_data(7 downto 0) <= pdata;
isa_state <= WRITE1_S;
else
isa_state <= IDLE_ISA_S;
end if;
when READ4_S =>
iochrdy <= '0';
isa_state <= READ4_WAIT_S;
when READ4_WAIT_S =>
iochrdy <= '1';
pdata <= isa_data_read(31 downto 24);
isa_state <= IDLE_ISA_S;
when WRITE1_S =>
if( iow = '1' ) then
iochrdy <= '1';
isa_state <= WRITE1_S;
else
isa_state <= WRITE2_IDLE_S;
end if;
when WRITE2_IDLE_S =>
if( ale = '1' ) then
if( paddr = isa_addr ) then
isa_state <= WRITE2_CHK_S;
elsif ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
isa_addr <= paddr;
isa_state <= READ_WRITE_S;
else
isa_state <= IDLE_ISA_S;
end if;
else
isa_state <= WRITE2_IDLE_S;
end if;
when WRITE2_CHK_S =>
if( ior = '1' ) then
iochrdy <= '0';
isa_rd <= '1';
isa_state <= READ1_S;
elsif( iow = '1') then
iochrdy <= '0';
isa_data(15 downto 8) <= pdata;
isa_state <= WRITE2_S;
else
isa_state <= IDLE_ISA_S;
end if;
when WRITE2_S =>
if( iow = '1' ) then
iochrdy <= '1';
isa_state <= WRITE2_S;
else
isa_state <= WRITE3_IDLE_S;
end if;
when WRITE3_IDLE_S =>
if( ale = '1' ) then
if( paddr = isa_addr ) then
isa_state <= WRITE3_CHK_S;
elsif ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
isa_addr <= paddr;
isa_state <= READ_WRITE_S;
else
isa_state <= IDLE_ISA_S;
end if;
else
isa_state <= WRITE3_IDLE_S;
end if;
when WRITE3_CHK_S =>
if( ior = '1' ) then
iochrdy <= '0';
isa_rd <= '1';
isa_state <= READ1_S;
elsif( iow = '1') then
iochrdy <= '0';
isa_data(23 downto 16) <= pdata;
isa_state <= WRITE3_S;
else
isa_state <= IDLE_ISA_S;
end if;
when WRITE3_S =>
if( iow = '1' ) then
iochrdy <= '1';
isa_state <= WRITE3_S;
else
isa_state <= WRITE4_IDLE_S;
end if;
when WRITE4_IDLE_S =>
if( ale = '1' ) then
if( paddr = isa_addr ) then
isa_state <= WRITE4_CHK_S;
elsif ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
isa_addr <= paddr;
isa_state <= READ_WRITE_S;
else
isa_state <= IDLE_ISA_S;
end if;
else
isa_state <= WRITE4_IDLE_S;
end if;
when WRITE4_CHK_S =>
if( ior = '1' ) then
iochrdy <= '0';
isa_rd <= '1';
isa_state <= READ1_S;
elsif( iow = '1') then
iochrdy <= '0';
isa_data(31 downto 24) <= pdata;
isa_wr <= '1';
isa_state <= WRITE4_S;
else
isa_state <= IDLE_ISA_S;
end if;
when WRITE4_S =>
iochrdy <= '0';
if( write_done = '1' ) then
isa_state <= WRITE4_WAIT_S;
else
isa_state <= WRITE4_S;
end if;
when WRITE4_WAIT_S =>
if( iow = '1' ) then
iochrdy <= '1';
isa_state <= WRITE4_WAIT_S;
else
isa_state <= IDLE_ISA_S;
end if;
when others =>
isa_state <= IDLE_ISA_S;
end case;
end if;
end process;
end BHV_CODEC_IM;
--*************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--*************************************************************************--
entity CODEC is
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027;
COMPRESSION : INTEGER:=1);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
pdata : inout UNSIGNED(7 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end CODEC;
--*************************************************************************--
architecture STR_CODEC of CODEC is
--
-- component declarations
--
component CODEC_IN
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027;
COMPRESSION : INTEGER:=1);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : in UNSIGNED(22 downto 0);
ib_wr : in STD_LOGIC;
ib_rd : in STD_LOGIC;
ib_valid : out STD_LOGIC );
end component;
component CODEC_IM
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : out UNSIGNED(22 downto 0);
ib_wr : out STD_LOGIC;
ib_rd : out STD_LOGIC;
ib_valid : in STD_LOGIC;
pdata : inout UNSIGNED(7 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end component;
--
-- component configurations
--
for all : CODEC_IN use entity WORK.CODEC_IN(BHV_CODEC_IN);
for all : CODEC_IM use entity WORK.CODEC_IM(BHV_CODEC_IM);
--
-- signals
--
signal ib_data : UNSIGNED(31 downto 0);
signal ib_addr : UNSIGNED(22 downto 0);
signal ib_wr, ib_rd, ib_valid : STD_LOGIC;
begin
--
-- component instantiations
--
U1 : CODEC_IN
generic map(IN_REG_ADDR,OUT_REG_ADDR,
STAT_REG_ADDR,CONT_REG_ADDR, COMPRESSION)
port map(clk, rst, ib_data, ib_addr, ib_wr, ib_rd, ib_valid);
U2 : CODEC_IM
generic map(IN_REG_ADDR,OUT_REG_ADDR,
STAT_REG_ADDR,CONT_REG_ADDR)
port map(clk, rst, ib_data, ib_addr, ib_wr,
ib_rd, ib_valid, pdata, paddr, ior, iow, ale, iochrdy);
end STR_CODEC;
--*************************************************************************--
--configuration CFG_CODEC of CODEC is
-- for STR_CODEC
-- end for;
--end CFG_CODEC;
-- end of file --
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