Xilinx FPGA Family Summaries

• Virtex Family

  • SRAM Based
  • Largest device has 1M gates
  • Configurable Logic Blocks (CLBs) have two 4-input LUTS, 2 DFFs
  • Four onboard Delay Locked Loops (DLLs) for clock synchronization
  • Dedicated RAM blocks (LUTs can also function as RAM).
  • Fast Carry Logic

• XC4000 Family

  • Previous version of Virtex
  • No DLLs, No dedicated RAM blocks

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